A SEU Tolerant CLB RAM for In-circuit Reconfiguration

Single Event Upsets (SEUs) are transient soft errors prominent in FPGA memories with radiation intensive environments. Hamming Error Correction Control (ECC) is a popular mechanism for SEU correction. However, Look Up Table (LUT) based Hamming designs make the ECC logic itself to be radiation prone. In this paper we propose an SEU tolerant Distributed RAM (ftDRAM) using Configurable Logic Blocks (CLBs) on the Xilinx Virtex FPGA families. Our ftDRAM incorporates unused CLB BlockRAMs for high speed On-Chip memories and SEU resistant Tri-State Buffers (BUFTs) for Hamming ECC. BUFTs are hardwired AND-OR logic elements within the Virtex fabric which are impervious to radiation upsets and BlockRAMs are LUT memories within a CLB which are often unused in typical designs. As a byproduct of this, we propose a novel, integrated In-Circuit Reconfiguration methodology for quick online SEU detection and correction using the ftDRAM. Device configuration data read back from the FPGA is compared at regular intervals with a copy of the original configuration stored in the ftDRAM. This helps in online SEU detection using simple BUFT based XOR comparators. In case of errors in the readback bitstream from the device, the correct configuration bits are written back from the ftDRAM. The ftDRAM which contains the original device configuration data is impervious to radiation errors owing to the Hamming ECC built into the design using the FPGA BUFTs. For typical LSI circuits, using our In-Circuit Reconfiguration methodology, we demonstrate a Mean Time To Repair (MTTR) of about 14.164ns which is very less compared to off-time specification in many high performance applications.