Concepts in Reliable and Optimal Systems Design

Designing reliable and optimal systems is one challenging goal in contemporary electronics. As technologies scale and information processing gets critical, reliability in high performance systems plays a vital role in maintaining prolonged uptime and dependable outputs. In this work, we provide insights into designing reliable systems with optimal configurations using a popular stochastic technique called the Genetic Algorithm (GA). GAs are highly tunable algorithms which work with large amounts of data and simple operators to yield optimal solutions to difficult problems. The thesis uses abstractions at the transistor, gate and systems level to demonstrate the heuristics and challenges in the same. In a transistor optimization problem the thesis propounds a novel technique for evolving transistor net lists directly from truth table descriptions of arbitrary digital circuits. A salient feature of the proposed technique is the bypassing of gate level representation and optimization in the VLSI design flow. This leads to generation of custom and semi-custom library cells on the fly. The second problem involves finding input vector pairs that cause maximum power dissipation in digital circuits. A modified genetic search and a vector partitioning approach are used to obtain good lower bounds for the same. GA heuristics for FIR Filters are presented in a third problem. The thesis demonstrates that the filters thus designed are self-adaptive; respond to arbitrary frequency response landscapes; have built-in coefficient error tolerance capabilities; and have a minimal adaptation latency. As a byproduct of this, it also proposes a novel flow for the complete hardware design of what is termed as an Evolutionary System on Chip (ESoC). Finally a fourth optimization problem outlines the design methodology of a SEU tolerant Distributed RAM using Configurable Logic Blocks (CLBs) on FPGAs incorporating unused CLB BlockRAMs for high speed On-Chip memories and SEU resistant Tri-State Buffers (BUFTs) for the ECC.